Generally, the background of the present invention is described in the "Phase-locked Loop Frequency Synthesizer" U.S. Pat. No. 4,360,788 granted to Floyd D. Erps and Raymond L. Fried on Nov. 23, 1982 and is incorporated herein by reference thereto.
Briefly, frequency synthesis encompasses various methods and apparatus wherein a frequency conversion process is utilized to translate the signal frequency of one or more reference signals to a large number of output signal frequencies that are relatively stable in frequency and relatively pure in spectral content, each of which output frequencies can be individually selected as the frequency of the synthesizer output signal.
One of the methods and apparatus for frequency synthesis utilizes an "indirect" technique in which a programmable divide-by-N phase-locked loop is used to achieve a desired output bandwidth and frequency resolution along with rapid switching speed and reduced level of noise suppression.
The programmable divide-by-N phase-locked loop is essentially a feedback system in which an error signal that is proportional to the phase difference between a feedback signal and a fixed reference signal is generated within a phase detector circuit. This error signal is low-pass filtered and utilized to control the frequency of a voltage controlled oscillator (VCO) circuit which supplies the synthesizer output signal. The synthesizer output signal is modified by a single sideband mixer and then divided in a programmable frequency divider circuit by a selectable factor, N, and then is fed to the phase detector. Since the phase-locked loop will synchronize when the error signal is zeroed by the phase of the feedback signal being substantially identical to the phase of the fixed reference signal, the VCO will supply the synthesizer output signal at a frequency N times the frequency of the fixed reference signal plus a minor offset frequency.
As part of the programmable frequency divider circuit, it has been common to use a two modulus prescaler which allows the programmable divide-by-N phase-locked loop to have a relatively high frequency resolution and relatively wide output bandwidth, e.g., one or more octaves. However, as time passes, it becomes more and more desirable to have very wide output bandwidth at a minimum expense and without affecting the switching speed or frequency resolution. Further, as the frequency range of desired signals increases, certain frequencies cannot be produced in a phase-locked loop system using only a two modulus prescaler.